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Samsung announced the start of production of chips with the process 3 nanometers (nm) thanks to the implementation of transistor architecture “Gate all around”(GAA), which improves energy efficiency
The technology behind
stacking technology GAA to which he resorted Samsung uses wider channel nanosheets instead of narrower channel nanowires to fabricate transistors, a design that improves power efficiency and performance.
This architecture is assembled under the name Multi-Bridge-Channel FET. (MBKFET), which lowers the supply voltage and increases the current capacity of the device, surpassing the benefits FinFET has offered so far as it collects Samsung this is a statement.
Application MBCFET in semiconductor manufacturing, it enables the production of 3nm transistors, which in the case of the first generation and compared to the 5nm lithography process reduces energy consumption by 45 percent and improves performance by 23%. The surface area is also reduced by 16%.
Samsung working on 3nm/GAAFET technology from 2019 and crisps The test prints were made last year, which means that the company has had more than enough time to do the necessary preparatory work before the announcement of the new lithograph. (According to Europe Press)
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I’m Liza Grey, an experienced news writer and author at the Buna Times. I specialize in writing about economic issues, with a focus on uncovering stories that have a positive impact on society. With over seven years of experience in the news industry, I am highly knowledgeable about current events and the ways in which they affect our daily lives.